Semiconductor device

ABSTRACT

A semiconductor device capable of high-speed read and has a high data-retention characteristic is provided. In a semiconductor device including a memory array having a plurality of memory cells provided at intersecting points of a plurality of word lines and a plurality of bit lines, where each memory cell includes an information memory section and a select element, when information is programmed by a first pulse (reset operation) for programming information flowing in the bit line and a second pulse (set operation) different from the first pulse and information is read by a third pulse (read operation), current directions of the second pulse and the third pulse are opposite to each other.

TECHNICAL FIELD

The present invention relates to a semiconductor device, and inparticular to an effective technique applied to a high-densityintegrated memory circuit including a memory cell discriminatingmemorized information items utilizing a different between resistances,for example, a memory cell using phase-change material, a logic-embeddedtype memory including a memory circuit and a logic circuit provided onthe same semiconductor substrate, or a semiconductor device having ananalog circuit. Especially, the present invention relates to ahigh-speed and nonvolatile random access memory which operates with alow voltage.

BACKGROUND ART

For example, growth of a nonvolatile memory market lead by demand formobile devices typified by mobile phones has been significant. A typicalexample of the nonvolatile memories is a FLASH memory, but since itsspeed is essentially slow, it is mainly used as a programmable ROM. Onthe other hand, a high-speed RAM is required as a working memory, andboth memories of the FLASH memory and a DRAM are mounted on a mobiledevice. If an element provided with features of the two memories isrealized, it is very impactful that in the points not only that itbecomes possible to integrate the FLASH memory and the DRAM on one chipbut also all the semiconductor memories are replaced.

One of candidates for realizing such an element is a nonvolatile memoryusing a phase-change film. A phase-change memory can also be calledPRAM, OUM, or ovonic memory. As already known, material which can bereversibly switched from a phase to the other phase is used for thephase-change memory. These phase states can be read out based upon adifferent in electric characteristic between both the phase states. Forexample, these materials can be changed between an irregular statecorresponding to an amorphous state and a regular state corresponding toa crystalline state. The amorphous state is higher in electricresistance than the crystalline state so that information can bememorized utilizing the difference in electric resistance.

Material suitable for the phase-change memory is alloy including atleast one element of sulfur, selenium, and tellurium, calledchalcogenide. Currently, the most promising chalcogenide is alloy(Ge₂Sb₂Te₅) comprising germanium, antimony, and tellurium, and it hasalready been widely used in an information memory section of arewritable optical disc. The chalcogenide is generally often p-type butit may be n-type according to a composition and/or a phase state, asshown in Patent Document 1.

As described above, memory of information is conducted utilizing adifference in phase state of chalcogenide. The phase change can beobtained by raising a temperature of the chalcogenide locally. Bothphases are stable in a temperature range of 70° C. to 130° C., whereinformation is retained. A data retention temperature for 10 years ofthe chalcogenide depends on its composition but it is generally in arange of 70 to 130° C. When data is retained for 10 years at atemperature exceeding the above temperature, phase change from anamorphous state to a thermodynamically stable crystalline state occurs.When the chalcogenide is retained for a sufficient period of time at acrystallization temperature of 200° C. or higher, a phase thereofchanges to reach a crystalline state. A crystallization time variesdepending on a composition of the chalcogenide and/or a temperature tobe held. In case of Ge₂Sb₂Te₅, for example, the crystallization time is150 ns (nanoseconds). In order to change the chalcogenide back to theamorphous state, the temperature of the chalcogenide is raised to amelting point (about 600° C.) or higher and rapidly cooled.

As a temperature-raising method, there is a method which causes currentto flow in chalcogenide to heat the chalcogenide by Joule heat generatedfrom an electrode inside or near the chalcogenide. Hereinafter,crystallizing chalcogenide of the phase change memory cells is calledset operation, while changing the chalcogenide to an amorphous state iscalled reset operation. A state where the phase-change portion has beencrystallized is called “set state”, while a state where the phase-changeportion has been made amorphous is called “reset state”. A set time is,for example, 150 ns, while a reset time is, for example, 50 ns.

A reading-out method is as follows: The resistance of chalcogenide isread and information items are identified by applying voltage tochalcogenide to measure current flowing through the chalcogenide. Atthis time, if the chalcogenide is put in the set state, even if thetemperature thereof is raised up to the crystallization temperature, theset state is held since the chalcogenide has been originallycrystallized. In case of the reset state, however, information isdestroyed. Therefore, read voltage must be set to small voltage of, forexample, 0.3V so as not to cause crystallization. A feature of thephase-change memory lies in that, since a resistance value of thephase-change portion changes according to a crystalline state or anon-crystalline state in a range of a double-digit value to atriple-digit value and a high side value and a low side value of theresistance value are read out while caused to correspond to binaryinformation items “0” and “1”, sensing operation is easily facilitatedaccording to increase of a resistance difference and reading isperformed at a high speed. Further, multi-value memory can be performedby causing the resistance difference to correspond to ternary or moreinformation. Hereinafter, the reading operation is called readoperation.

Next, the phase-change memory cells based upon the abovementioned willbe explained with reference to FIGS. 35 to 37. Note that, FIGS. 35 to 37show diagrams of a phase-change memory cell which has been examined bythe present inventors, FIG. 35 shows a circuit configuration of thephase-change memory cell, FIG. 36 shows a structure thereof, and FIG. 37shows an operating method thereof.

A phase-change memory cell 111 often comprises an information memorysection 113 and a selection transistor 109, but a cross-point typememory cell which does not include a selection transistor is alsothought. The information memory section 113 includes a chalcogenide 112,and a top electrode 115 and a plug electrode 114 sandwiching the same.Generally, the plug electrode 114 often takes a plug structure having acontact area with the chalcogenide smaller than a contact area of thetop electrode 115, but there is such a case that a thin film is used asthe electrode, as shown in Non-Patent Document 1.

A common operation of the phase-change memory is described in non-PatentDocument 2. The reset operation is performed by raising a word line toapply current pulse having a pulse width of 20 to 50 ns to a bit line.The set operation is performed by raising a word line to apply currentpulse having a pulse width of 60 to 200 ns to a bit line. The readoperation is performed by raising a word line to apply current pulsehaving a pulse width of 20 to 100 ns to a bit line. Current pulses usedin the reset operation, the set operation, and the read operation flowfrom a bit line toward a source line in all the operations, as shown inFIGS. 35 to 37, or they flow from the source line to the bit line in allthe operations.

In this case, as compared with the set operation where temperaturerising up to the crystallization temperature is conducted, currentlarger than that in the set operation is required in the reset operationwhere heating must be conducted to at least the melting point which ishigher than the crystallization temperature. By reducing reset operationcurrent, an area of a select element is reduced so that high integrationof a memory is made possible.

Patent Document 1: U.S. Pat. No. 3,983,076

Non-Patent Document 1: 2003 Symposium on VLSI Technology, pages 175 to176, Digest of Technical Papers

Non-Patent Document 2: 2004 ISSCC, pages 40 to 41, Digest of TechnicalPapers

DISCLOSURE OF THE INVENTION

Now, the semiconductor memory is generally required to retain data for10 years in a temperature range of 70 to 120° C. On the other hand, a10-years data retention temperature of chalcogenide depends on thecomposition of the chalcogenide but it is generally in a temperaturerange of 70 to 130° C.

Therefore, in order to conduct the read operation without destroyinginformation, it is necessary to hold the temperature of the chalcogenidein a temperature equal to or lower than the 10-years data retentiontemperature even if the read operation is performed. On the other hand,temperature rising up to a high temperature where phase change occurs ina short period of time at a reprogramming time is performed with anallowable voltage in the semiconductor circuit, for example, 1.5V.Therefore, voltage which can be used for read must be suppressed to alow voltage such as 0.3V, for example. Thus, such a problem arises thata reading speed lowers.

Since reset operation current is large, such a problem also arises thatdegree of integration is limited.

In view of these circumstances, an object of the present invention is tosolve the above problems and provide a technique for realizing asemiconductor device which can perform reading-out at a high speed andhas high data retention characteristic.

The above and other objects and novel characteristics of the presentinvention will be apparent from the description of this specificationand the accompanying drawings.

The typical ones of the inventions disclosed in this application will bebriefly described as follows.

The present invention is applied to a semiconductor device including amemory array including a plurality of memory cells provided atintersecting points between a plurality of word lines and a plurality ofbit lines, each memory cell comprising an information memory section anda select element, where, when programming of information is performed byfirst pulse (reset operation) for programming information flowing in abit line and second pulse (set operation) different from the first pulseand information is read out by third pulse (read operation), currentdirections of the second pulse and the third pulse are opposite to eachother.

In the semiconductor device according to the present invention, theinformation memory section comprises a first electrode of a topelectrode, a memory element, a semiconductor material, and a secondelectrode of a plug electrode, where p-n junction is present in aninterface between the memory element and the semiconductor material, orthe information memory section comprises a first electrode, a memoryelement, a dielectric material, and a second electrode, and non-ohmicelectric resistance is present in an interface between the memoryelement and the dielectric material.

The effects obtained by typical aspects of the present invention will bebriefly described below.

According to the present invention, a semiconductor device which canconduct high-speed reading-out and has high data retentioncharacteristic can be realized.

BRIEF DESCRIPTIONS OF THE DRAWINGS

FIG. 1 is a diagram showing a circuit configuration of a phase-changememory cell according to an embodiment of the present invention;

FIG. 2 is a diagram showing a structure of the phase-change memory cellaccording to the embodiment of the present invention;

FIG. 3 is a diagram showing an operating method of the phase-changememory cell according to the embodiment of the present invention;

FIG. 4 is a diagram showing a cross-sectional structure of aninformation memory section in a phase-change memory cell according to afirst embodiment of the present invention;

FIG. 5 is a diagram showing a current-voltage waveform obtained whenvoltage higher than that applied to a plug electrode is applied to a topelectrode in the phase-change memory cell according to the firstembodiment of the present invention;

FIG. 6 is a diagram showing a current-voltage waveform obtained whenvoltage higher than that applied to the top electrode is applied to theplug electrode in the phase-change memory cell according to the firstembodiment of the present invention;

FIG. 7 is a circuit diagram schematically showing the phase-changememory cell according to the first embodiment of the present inventionwhen voltage higher than that applied to a plug electrode is applied toa top electrode;

FIG. 8 is a circuit diagram schematically showing the phase-changememory cell according to the first embodiment of the present inventionwhen voltage higher than that applied to the top electrode is applied tothe plug electrode;

FIG. 9 is a diagram showing influences imparted to a set operation and aread operation of an information memory section by current directions inthe phase-change memory cell according to the first embodiment of thepresent invention;

FIG. 10 is a layout diagram of main parts in a portion where respectivemembers configuring a phase-change memory cell are arranged in amanufacturing method of a phase-change memory cell according to thefirst embodiment of the present invention;

FIG. 11 is a layout diagram of main parts in a portion where respectivemembers configuring a phase-change memory cell are arranged in amanufacturing method of a phase-change memory cell according to thefirst embodiment of the present invention;

FIG. 12 is a layout diagram of main parts in a portion where respectivemembers configuring a phase-change memory cell are arranged in amanufacturing method of a phase-change memory cell according to thefirst embodiment of the present invention;

FIG. 13 is a cross-sectional view of a main portion taken along lineX-X′ in FIGS. 10 to 12 in the manufacturing method of a phase-changememory cell according to the first embodiment of the present invention;

FIG. 14 is a cross-sectional view of a main portion taken along lineX-X′ in FIGS. 10 to 12 in the manufacturing method of a phase-changememory cell according to the first embodiment of the present invention;

FIG. 15 is a cross-sectional view of a main portion taken along lineX-X′ in FIGS. 10 to 12 in the manufacturing method of a phase-changememory cell according to the first embodiment of the present invention;

FIG. 16 is a cross-sectional view of a main portion taken along lineX-X′ in FIGS. 10 to 12 in the manufacturing method of a phase-changememory cell according to the first embodiment of the present invention;

FIG. 17 is a cross-sectional view of a main portion taken along lineX-X′ in FIGS. 10 to 12 in the manufacturing method of a phase-changememory cell according to the first embodiment of the present invention;

FIG. 18 is a cross-sectional view of a main portion taken along lineX-X′ in FIGS. 10 to 12 in the manufacturing method of a phase-changememory cell according to the first embodiment of the present invention;

FIG. 19 is a cross-sectional view of a main portion of an applicationexample in the manufacturing method of a phase-change memory cellaccording to the first embodiment of the present invention;

FIG. 20 is a cross-sectional view of a main portion of the applicationexample in the manufacturing method of a phase-change memory cellaccording to the first embodiment of the present invention;

FIG. 21 is a layout diagram of main parts in a portion where respectivemembers configuring a phase-change memory cell are arranged in amanufacturing method of a phase-change memory cell according to a secondembodiment of the present invention;

FIG. 22 is a layout diagram of main parts in a portion where respectivemembers configuring a phase-change memory cell are arranged in amanufacturing method of a phase-change memory cell according to thesecond embodiment of the present invention;

FIG. 23 is a layout diagram of main parts in a portion where respectivemembers configuring a phase-change memory cell are arranged in amanufacturing method of a phase-change memory cell according to thesecond embodiment of the present invention;

FIG. 24 is a cross-sectional view of a main portion taken along lineX-X′ in FIGS. 21 to 22 in the manufacturing method of a phase-changememory cell according to a second embodiment of the present invention;

FIG. 25 is a cross-sectional view of a main portion taken along lineY-Y′ in FIGS. 21 to 12 in the manufacturing method of the phase-changememory cell according to the second embodiment of the present invention;

FIG. 26 is a layout diagram of main parts of an application example ofthe manufacturing method of a phase-change memory cell according to thesecond embodiment of the present invention;

FIG. 27 is a layout diagram of main parts in a portion where respectivemembers configuring a phase-change memory cell are arranged in amanufacturing method of a phase-change memory cell according to a thirdembodiment of the present invention;

FIG. 28 is a layout diagram of main parts in a portion where respectivemembers configuring a phase-change memory cell are arranged in themanufacturing method of a phase-change memory cell according to thethird embodiment of the present invention;

FIG. 29 is a layout diagram of main parts in a portion where respectivemembers configuring a phase-change memory cell are arranged in amanufacturing method of a phase-change memory cell according to a fourthembodiment of the present invention;

FIG. 30 is a layout diagram of main parts in a portion where respectivemembers configuring a phase-change memory cell are arranged in themanufacturing method of a phase-change memory cell according to thefourth embodiment of the present invention;

FIG. 31 is a layout diagram of main parts in a portion where respectivemembers configuring a phase-change memory cell are arranged in amanufacturing method of a phase-change memory cell according to a fifthembodiment of the present invention;

FIG. 32 is a layout diagram of main parts in a portion where respectivemembers configuring a phase-change memory cell are arranged in themanufacturing method of a phase-change memory cell according to thefifth embodiment of the present invention;

FIG. 33 is a circuit diagram configuring a main portion of a memorymodule including a phase change memory cell according to a sixthembodiment of the present invention;

FIG. 34 is a diagram showing programming and reading operations in amemory module including the phase-change memory cell according to thesixth embodiment of the present invention;

FIG. 35 is a diagram showing a circuit configuration of a phase-changememory cell which has been examined by the inventors;

FIG. 36 is a diagram showing a structure of the phase-change memory cellwhich has been examined by the inventors; and

FIG. 37 is a diagram showing an operating method of the phase-changememory cell which has been examined by the inventors.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described indetail with reference to the accompanying drawings. Note that,components having the same function are denoted by the same referencesymbols throughout the drawings for describing the embodiment, and therepetitive description thereof will be omitted.

CONCEPT OF EMBODIMENTS

One example of a phase-change memory cell according to an embodiment ofthe present invention will be explained with reference to FIGS. 1 to 3.FIGS. 1 to 3 are diagrams and a view showing a phase-change memory cellin an embodiment, FIG. 1 is a diagram showing a circuit configuration ofthe phase-change memory cell, FIG. 2 is a structure thereof, and FIG. 3is a diagram showing an operating method thereof.

As shown in FIG. 1, a phase-change memory cell 101 comprises aninformation memory section 103 and a selection transistor (selectelement) 109. One end of the information memory section 103 is connectedto a bit line BL and the other end thereof is connected to the selectiontransistor 109. The drain of the selection transistor 109 is connectedto information memory section 103, the source thereof is connected to asource line SL, and the gate thereof is connected to a word line WL. Asthe select element, a MISFET such as a MOSFET, a bipolar transistor, ora junction can be used.

As shown in FIG. 2, in the phase-change memory cell 101, the informationmemory section 103 has such a structure that a chalcogenide (memoryelement) 102 is sandwiched between a top electrode (a first electrode)105 and a plug electrode (a second electrode) 104. As the memoryelement, a phase-change element (variable resistor) whose resistancevalue changes according to its crystalline state is used. As materialfor the phase-change element, chalcogenide is used herein. Note that, inFIG. 2, reference numeral 106 denotes a word line (WL), 107 denotes acontact connecting the source line (SL) and the source of the selectiontransistor 109 to each other, and 108 denotes a contact connecting thebit line (BL) and the top electrode 105 to each other.

As shown in FIG. 3, a reset operation (“0”-programming) is performed byraising the word line (voltage: for example, 1.5V) and applying current(Irs: for example, 200 μA) pulse having a pulse width of Trs (forexample, about 50 ns) to the bit line. A set operation (“1”-programming)is performed by raising the word line (voltage: for example, 1.5V) andapplying current (Is: for example, 100 μA) pulse having a pulse width ofTs (for example, about 150 ns) to the bit line. A read operation isperformed by raising the word line and applying current pulse (Ir: forexample, 60 μA) having a pulse width of Tr (for example, about 10 ns) tothe bit line.

In this case, the set operation is performed by causing current to flowin a direction (A→B) from the top electrode 105 to the plug electrode104, while the read operation is performed by causing current to flow ina direction (B→A) from the plug electrode 104 to the top electrode 105.When the phase-change memory cell 101 is at least in the reset state,non-ohmic interface resistance is present between the top electrode 105or the plug electrode 104 and the chalcogenide 102.

For example, as described in detail later (FIG. 8 and the like), whencurrent is caused to flow in an opposite direction to the non-ohmicinterface resistance at the read time, since voltage drop occurs in thenon-ohmic interface resistance, voltage applied to the chalcogenide 102lowers. As a result, destruction of information due to reading isprevented. In the set operation, drop of voltage in the non-ohmicinterface is avoided by causing current to flow in a forward directionof the non-ohmic interface, so that driving voltage at a set operationtime can be reduced.

First Embodiment

One example of a phase-change memory cell according to a firstembodiment of the present invention will be explained in detail belowwith reference to FIGS. 4 to 20.

FIG. 4 shows a cross-sectional structure of an information memorysection of a phase-change memory cell. In the information memory section103, the chalcogenide 102 is sandwiched between the top electrode 105and the plug electrode 104. A composition of the chalcogenide 102 isGe₂Sb₂Te₅, and compositions of the plug electrode 104 and the topelectrode 105 are tungsten. A size 141 of the plug electrode 104 is adiameter of 160 nm. Note that, the size 141 of the plug electrode 104may vary according to generation of a semiconductor process to be used.As a composition of the top electrode 105, tungsten is often used, butconductive material can be used as the top electrode.

Experimental results where current has been caused to flow between thetop electrode 105 shown by symbol “A” in FIG. 4 and the plug electrode104 shown by symbol “B” in FIG. 4 and voltage values between A and Bhave been measured are shown in FIGS. 5 and 6.

This experiment is performed in the reset state of the informationmemory section 103. A waveform obtained when a voltage higher than thatapplied to the plug electrode 104 is applied to the top electrode 105(V_(A)>V_(B)), that is, when current is caused to flow from the topelectrode 105 to the plug electrode 104 through the chalcogenide 102 isshown in FIG. 5. This experiment shows the following fact. A resistanceof the information memory section 103 is calculated by dividing voltageby current. It is understood that, when the applied voltage exceeds 1.7Vwhich is a threshold voltage 211, the resistance of the informationmemory section 103 lowers rapidly so that the chalcogenide 102phase-changes from an amorphous state to a crystalline state. That is,it is understood that, when current is caused to flow from the topelectrode 105 to the plug electrode 104, the threshold voltage 211 wherethe set operation is performed is 1.7V.

Next, A waveform obtained when voltage higher than that applied to thetop electrode 105 is applied to the plug electrode 104 (V_(A)<V_(B)),that is, when current is caused to flow from the plug electrode 104 tothe top electrode 105 via the chalcogenide 102 is shown in FIG. 6. Inthis experiment, it is understood that, when the applied voltage exceedsa threshold voltage 212, the chalcogenide 102 phase-changes from theamorphous state to the crystalline state. At this time, the thresholdvoltage 212 is 2.3V and it is higher than the threshold voltage 211.

The reason is explained in the following manner. A chalcogenide in anamorphous state is generally a p-type semiconductor. Therefore,non-ohmic interface resistance is formed in an interface between anelectrode and the chalcogenide. The interface resistance configures aSchottky barrier diode when the electrode is made from metal material.Since a contact area between the chalcogenide 102 and the plug electrode104 is smaller than that between the chalcogenide 102 and the topelectrode 105, influence of the non-ohmic interface resistance becomeslarge.

A circuit diagram when voltage higher than that applied to the plugelectrode 104 is applied to the top electrode 105 (V_(A)>V_(B)) isschematically shown in FIG. 7. A resistance of the chalcogenide 102 isshown by a circuit symbol 215, and an interface resistance is shown by acircuit symbol 214. The interface resistance has electric characteristicwhere a diode and a resistor are connected in parallel. Sinceapplication voltage 213 is applied in a forward direction of a diodecontained in the interface resistance 214, the interface resistance 214is low resistance and almost all of the application voltage 213 isapplied to a resistance 215 of the chalcogenide.

A circuit diagram when voltage higher than that applied to the topelectrode 105 is applied to the plug electrode 104 (V_(A)<V_(B)) isschematically shown in FIG. 8. In this case, since voltage is applied ina backward direction to the diode contained in the interface resistance214, the interface resistance 214 is high resistance. Therefore,application voltage 216 is applied separately to the resistance 215 ofthe chalcogenide and the interface resistance 214. Accordingly, voltageapplied to the resistance 215 of the chalcogenide becomes low.

From the above, as shown in FIG. 9, the read operation is performed bycausing current to flow from the plug electrode 104 to the top electrode105 so that destruction of information can be prevented. The setoperation is performed by causing current to flow from the top electrode105 to the plug electrode 104 so that the set voltage can be reduced tolow voltage. According to kinds of chalcogenide materials, current orvoltage used for the set operation or the reset operation can be madelower than those used for the read operation. As a result, the readoperation can be made high speed.

An NMOSFET has such a feature that driving current thereof is largerthan that for a PMOSFET. When the NMOSFET is used as the selectiontransistor 109, the reset operation is performed by causing current toflow from the top electrode 105 to the plug electrode 104, as shown inFIGS. 1 to 3, so that the following effect can be obtained. Since asource voltage of the NMOSFET can be made equal to potential of thesource line SL, voltage between the gate and the source becomes large.Therefore, an area of the NMOSFET required to obtain the same resetcurrent can be reduced. If current is caused to flow from the plugelectrode 104 to the top electrode 105, voltage drop occurs in theinformation memory section 103, so that the source potential of theNMOSFET becomes higher than the potential of the source line SL.Therefore, driving ability of the NMOSFET lowers.

When non-ohmic resistance is formed between the chalcogenide 102 and theplug electrode 104, such a merit can be obtained that a reading signalis amplified. As understood from FIGS. 5 and 6, this is becauseinterface resistance between the plug electrode and the chalcogenide inamorphous state is generally larger than that between the plug electrodeand the chalcogenide in a crystalline state so that when the informationmemory section 103 is in the reset state, resistance becomes furtherhigh due to presence of the interface resistance, but when theinformation memory section 103 is in the set state, the resistancehardly changes so that a resistance ratio of the set state and the resetstate becomes large and a reading signal becomes large. As a result,high-speed reading is made possible.

Next, when the contact area between the top electrode 105 and thechalcogenide 102 is equal to that between the plug electrode 104 and thechalcogenide 102, a current direction suitable for the set operation anda current direction suitable for the read operation can be madedifferent by making material for the top electrode 105 and material forthe plug electrode 104 different from each other. Further,non-destructive reading can be performed using pulse having voltageamplitude or current amplitude larger than that of pulse used for theset operation by reversing current directions of the set operation andthe read operation to each other.

Subsequently, one example of a manufacturing method of a phase-changememory cell will be explained with reference to FIG. 10 to FIG. 20.FIGS. 10 to 12 show layout diagrams of a main portion in a portion whererespective members configuring a phase-change memory cell are arranged,FIGS. 13 to 18 show cross-sectional views of a main portion taken alongline X-X′ in FIGS. 10 to 12, and FIGS. 19 and 20 show cross-sectionalviews of a main portion of an application example.

FIG. 10 shows a source line SL and a bit line BL. An optimal distancebetween the source line SL and the bit line BL is selected according todriving current of a memory cell.

FIG. 11 shows a plug electrode 301, a word line WL, a source line SL,and a bit line BL.

FIG. 12 shows an active region 303 and a contact 302 with the activeregion.

First, a structure shown in FIG. 13 is produced using ordinarysemiconductor manufacturing steps. A diffusion layer 320 is separated bya field oxide layer 311. A gate electrode 314 contacts with a gateinsulation film 312, sidewalls 313, and a metal silicide 315. In orderto improve adhesion between a contact 317 and an interlayer insulationfilm 319 and prevent peeling-off, an adhesion layer 316 is formed. Thecontact 317 is connected to a metal wire 318.

Next, as shown in FIG. 14, a contact hole is formed, and an adhesionlayer 332 and a plug electrode 331 are formed in the contact hole bychemical vapor deposition (CVD). As material for the plug electrode 331,material forming non-ohmic contact between the same and chalcogenide isselected. By using material with high thermal resistance, diffusion ofJoule heat from the plug electrode is prevented, and power required forreprogramming can be reduced. As a composition of the adhesion layer332, TiN can be used, and W can be used as a composition of material forthe plug electrode 331.

As shown in FIG. 15, films of chalcogenide 341 and a top electrode 342are formed by sputtering or vacuum deposition, and an interlayerinsulation film 343 is formed. As a composition of the chalcogenide 341,alloy of Ge—Sb—Te which has wide credential as a recording type opticaldisc, or the alloy including additive is suitable.

Next, as shown in FIG. 16, a contact hole is formed and an adhesionlayer 350 and a contact 351 with a bit line are formed by chemical vapordeposition (CVD).

Further, as shown in FIG. 17, an adhesion layer 352 is formed and a bitline 353 is sputtered.

Subsequently, as shown in FIG. 18, it is possible to manufacture adesired phase-change memory cell by forming an interlayer insulationfilm 363 and further forming a top electrode. Note that, in FIG. 18,reference numeral 364 denotes a portion corresponding to the informationmemory section shown in FIG. 4.

In the present embodiment, it is possible to conduct manufacturepursuant to an ordinary CMOS logic embedded design rule, and theembodiment can be applied to manufacture of a logic embedded memory.

As shown in FIG. 19, a structure where a heater layer 365 is sandwichedbetween the plug electrode 331 and the adhesion layer 332, and thechalcogenide 341 can be taken. The heater layer 365 has electricresistance higher than that of the plug electrode 331, and current isefficiently converted to Joule heat in the heater layer 365 at areprogramming operation time. Further, non-ohmic interface resistance ispresent between the heater layer 365 and the chalcogenide 341, so thathigh-speed reading is made possible. It is preferable that the non-ohmicinterface resistance is formed by Schottky junction or p-n junction.When the p-n junction is formed, the heater layer 365 is made fromsemiconductor material.

As shown in FIG. 20, such a structure where a bonding layer 366 issandwiched between the plug electrode 331 and the adhesion layer 332,and the chalcognide 341 can be taken. The bonding layer 366 hasexcellent bonding force to the interlayer insulation film 363, the plugelectrode 331, and the chalcogenide 341, and it can prevent peeling-offof the chalcogenide and occurrence of a depletion portion in thechalcogenide during a manufacture step, and occurrence of a depletionportion in the chalcogenide during memory cell operation. As a result,yield and programming reliability during manufacture are improved. Thenon-ohmic interface resistance is present between the bonding layer 366and the chalcogenide 341, so that high-speed reading operation is madepossible. It is preferable that the bonding layer 366 is made fromdielectric material.

Second Embodiment

One example of a phase-change memory cell according to a secondembodiment of the present invention will be explained in detail withreference to FIGS. 21 to 26. FIGS. 21 to 23 show layout diagrams of amain portion in a portion where respective members configuring aphase-change memory cell are arranged, FIG. 24 shows a cross-sectionalview of a main portion taken along line X-X′ in FIGS. 21 to 22, FIG. 25shows a cross-sectional view of a main portion taken line Y-Y′ in FIGS.21 to 22, and FIG. 26 shows a layout diagram of main parts of anapplication example.

The second embodiment is an example of an application to a structure ofa phase-change memory cell with high integration degree, and it will beexplained below.

FIG. 21 shows an active region 303, a source line SL, the word line WL,and a plug electrode 301 contacting with a chalcogenide. When a minimumworking size is represented by F, a word line spacing is 2F, and asource line spacing is 3F. FIG. 22 shows the active region 303, the wordline WL, a bit line BL, and the plug electrode 301 contacting with thechalcogenide. Further, FIG. 23 shows the contact 361 with the sourceline.

In FIGS. 24 and 25, a plug electrode 331 is formed using a sidewall 313in a self-aligning manner. It is preferable that material for thesidewall 313 is material having large selection ratio to an interlayerinsulation film 343 at processing. A bit line denoted by referencenumeral 342 is used as a top electrode of a chalcogenide 341.

The second embodiment is low regarding consistency with a CMOS logicdesign rule, but it is possible to set a memory cell area to 6F², sothat the second embodiment is suitable for a stand-alone memory with alarge capacity.

As shown in FIG. 26, such a configuration can be adopted that a bit lineBL is disposed and a top electrode of the chalcogenide is utilized as asource line. In this case, since separation of the source line is notperformed, fine working to the source line is not required, so that itis possible to reduce damage to the chalcogenide due to the working.Thereby, it becomes possible to manufacture a phase-change memory cellwith high reliability.

Third Embodiment

One example of a phase-change memory cell according to a thirdembodiment of the present invention will be explained in detail withreference to FIGS. 27 and 28. FIGS. 27 and 28 show layout diagrams of amain portion in a portion where respective members configuring aphase-change memory cell are arranged.

The third embodiment is an example where the present invention has beenapplied to a structure in which both high integration and reliability ofa phase-change memory cell are achieved, and it will be explained below.

FIG. 27 shows an active region 303, a plug electrode 301, and a contact361 with a source line. Further, a bit line BL and a word line WL areshown in FIG. 28. A word line spacing is 2F and a bit line spacing is4F. An area of a memory cell is 8F². Since the structure can take largebit line spacing, such a merit can be obtained that it is easy toconduct separation of chalcogenide. Thereby, both high integration andhigh reliability can be achieved.

Fourth Embodiment

One example of a phase-change memory cell according to a fourthembodiment of the present invention will be explained in detail withreference to FIGS. 29 and 30. FIGS. 29 and 30 show layout diagrams of amain portion in a portion where respective members configuring aphase-change memory cell are arranged.

The fourth embodiment is an example where the present invention has beenapplied to a structure of a phase-change memory cell which can operateat higher speed, and it will be explained below.

FIG. 29 shows a bit line BL, a word line WL, a plug electrode 301, and acontact 361 with a source line. Further, FIG. 30 shows an active region303. A merit of this structure lies in that high-speed operation can beperformed since a word line length can be reduced.

Fifth Embodiment

One example of a phase-change memory cell according to a fifthembodiment of the present invention will be explained in detail withreference to FIGS. 31 and 32. FIGS. 31 and 32 show layout diagrams of amain portion in a portion where respective members configuring aphase-change memory cell are arranged.

The fifth embodiment is an example where the present invention has beenapplied to a structure of a phase-change memory cell which can operatewith an optimal current amount, and it will be explained below.

FIG. 31 shows a bit line BL, a plug electrode 301, a word line WL, acontact 361 with a source line, and an active region 303. FIG. 32 showsa region defining the active region 303 clearly. A merit of thestructure lies in that, since two transistors are used in one memorycell, one transistor is used for the set operation and two transistorsare used for the reset operation so that the respective operations canbe performed with corresponding optimal current amounts.

Sixth Embodiment

One example of a memory module including a phase-change memory cellaccording to a sixth embodiment of the present invention will beexplained with reference to FIGS. 33 and 34.

FIG. 33 shows a circuit diagram configuring a main portion of a memorymodule including a phase-change memory. In the sixth embodiment, thememory module comprises a memory array section MA, an X-system addressdecoder X-DEC, a Y-system address decoder Y-DEC, a reading/programmingcircuit RWC, and the like.

The memory array section MA comprises a plurality of bit lines BL (BL0to BLm), a plurality of source lines SL (SL0 to SLm), and a plurality ofword lines WL (WL0 to WLn), and memory cells MC (MC00 to MCnm) areconnected to intersecting points of respective bit lines BL with therespective word lines WL. The respective memory cells MC comprise selectelements MN (MN00 to MNnm) and memory elements R (R00 to Rnm). Thememory element R is a phase-change element and it has a low resistancein a range of 1 kΩ to 10 kΩ in a crystalline state, while it has a highresistance in a range of 100 kΩ to 100 MΩ in an amorphous state. Theselect element MN is an N-channel type MOSFET. For example, the gateelectrode of the select element MN00 is connected to the word line WL0,the drain electrode thereof is connected to the memory element R00, andthe source electrode thereof is connected to the source line SL0.Connections of the remaining select elements are similarly conducted.

Note that, in the present embodiment, the MOSFET is used as the selectelement, but a bipolar transistor may be used instead of the MOSFET. Inthis case, since driving ability of the select element per unit area ishigh, such a merit can be obtained that the memory cell area can bereduced.

The X-system address decoder X-DEC is connected with the word lines WL,and one word line WL is selected by an X-system address signal. TheY-system address decoder Y-DEC is connected to one ends of the bit linesBL and the source lines SL, and a set of bit line BL and source line SLis selected by a Y-system address signal to be connected to thereading/programming circuit RWC described later.

Note that, in the present embodiment, one reading/programming circuitRWC is provided for each of the memory array sections MA, but aplurality of reading/programming circuits may be provided for eachmemory array section, of course. In this case, since reading/programmingoperation can be simultaneously performed to a plurality of bits, suchan effect can be obtained that high-speed operation can be madepossible.

The reading/programming circuit RWC comprises a sense amplifier SA, areading current source Iread, a reset switch RS-SW for the readingcurrent source Iread, a reset current source Ireset, a reset switchRS-SW for the reset current source Ireset, a set current source Iset, aset switch SS-SW for the set current source Iset, a programming groundswitch WG-SW, and the like. The current sources Iread, Iset, and Iresetare connected to a read operation voltage source Vread, a set operationvoltage source Vset, and a reset operation voltage source Vreset,respectively. A sense amplifier enabling signal SE, a reference voltageREF, and a data output line D are connected to the sense amplifier SA.

In the present embodiment, programming/reading operations will beexplained with reference to FIG. 34. As one example, an operation of thememory cell MC00 will be described. Operations of the other memory cellsare conducted similarly.

The reset operation (RESET) is performed in the following manner. Theread switch RSW and the set switch SS-SW are put in OFF state. First,the reset switch RS-SW and the programming ground switch WG-SW areturned ON. The memory cell MC00 is selected by the X-system addressdecoder X-DEC and the Y-system address decoder Y-DEC so that currentlarger than set current described later is caused to flow in the memorycell MC00. After the current is caused to flow for a fixed period oftime, the word line WL0 and the bit line BL0 are caused to fall down.Thereby, the memory element R00 is rapidly cooled from a melted state tobecome amorphous.

The set operation (SET) is performed in the following manner. The readswitch RSW and the reset switch RS-SW are put in OFF state. First, theset switch SS-SW and the programming ground switch WG-SW are turned ON.The memory cell MC00 is selected by the X-system address decoder X-DECand the Y-system address decoder Y-DEC so that current smaller than forthe abovementioned reset operation is caused to flow in the memory cellMC00. After current is caused to flow for a period of time longer thanthat in the abovementioned reset operation, the word line WL0 and thebit line BL0 are caused to fall down. Thereby, the memory element R00 iscrystallized.

Since programming is performed in a current direction where the state ofthe memory element easily changes in the set operation, information inthe memory element is easily rewritten. The reset operation is performedby causing current to flow in a direction in which the source potentialof the NMOSFET can be made equal to that of the source line and voltagebetween the gate and the source of the NMOSFET can be made large, thatis, from the bit line to the source line through the memory cell.

The read operation (READ) is performed in the following manner. Thereset switch RS-SW, the programming ground switch WG-SW, and the setswitch SS-SW are turned OFF. First, the read switch RSW is turned ON.After a predetermined period of time, the read switch RSW is turned OFF.Current corresponding to a resistance value of the memory element R00flows in the memory element R00 so that the bit line is charged. Thatis, when the memory element R00 is in a low resistance, the bit line BL0is charged to a voltage higher than that at the time when the bit lineBL0 is in the high resistance. By turning the sense amplifier enablingsignal SE ON, the potential difference is amplified by the senseamplifier SA, so that data can be obtained from the data output line D.

Unlike the set operation, since reading is performed in the readoperation by causing current to flow in a direction in which the stateof the memory element hardly changes, information in the memory elementis hardly destroyed.

The current amount required for the operation depends on thecharacteristics of the memory element. For explanation, specificnumerical examples are described below. For example, when the resetcurrent is 200 μA (micro ampere), chalcogenide can be melted. The pulsewidth of this reset current is 50 ns (nanoseconds). For example, whenthe set current is 100 μA, the temperature of chalcogenide can be raisedto the crystallization temperature of higher. The pulse width of the setcurrent is 150 ns. When such a configuration is adopted that, when thememory cell is in the set state, for example, the read current of 60 μAflows, the reading operation can be performed with a practical speed.Such setting can be performed that, when the memory cell is in the resetstate, for example, the read current is only 1 μa. The pulse width ofthe read current is 10 ns.

EFFECT OF EMBODIMENTS

According to the respective embodiments described above, a semiconductordevice which can perform high-speed reading and has high data retentioncharacteristic, especially, a semiconductor nonvolatile memory can berealized. Further, the semiconductor nonvolatile memory can provide alogic embedded type memory such as a high-functional incorporated-typemicrocomputer with high reliability or a semiconductor device includingan analog circuit by mounting the semiconductor nonvolatile memory and alogic circuit such as a CPU on the same substrate in a mixing manner.The semiconductor nonvolatile memory can also be provided as astand-alone memory.

In the foregoing, the invention made by the inventors of the presentinvention has been concretely described based on the embodiments.However, it is needless to say that the present invention is not limitedto the foregoing embodiments and various modifications and alterationscan be made within the scope of the present invention.

INDUSTRIAL APPLICABILITY

A technique for realizing stable programming of a phase-change memoryaccording to the present invention widely contributes practical use ofthe phase-change memory and, especially, such a possibility that thephase-change memory can be widely used in a nonvolatile-memory embeddedMemory microcomputer, an IC card or the like is considerably high. Thatis, according to significant spreading of mobile devices, demand fornon-volatile memories increases. Especially, such a memory to beembedded with a logic circuit is easy, high-speed programming can beperformed, the number of writable times is large, and driving voltage islow is demanded. The phase-change memory can be utilized as a memoryhaving all the features described above.

1. A semiconductor device including a memory array comprising aplurality of memory cells provided at intersecting points of a pluralityof word lines and a plurality of bit lines intersecting the plurality ofword lines via an insulating layer, each memory cell including aninformation memory section and a select element, wherein whenprogramming of information is performed by a first pulse which programsinformation flowing in the bit line and a second pulse different fromthe first pulse and information is read by a third pulse, currentdirections of the second pulse and the third pulse are opposite to eachother.
 2. The semiconductor device according to claim 1, wherein theselect element is a MISFET.
 3. The semiconductor device according toclaim 1, wherein the select element is a bipolar-type transistor.
 4. Thesemiconductor device according to claim 1, wherein the select element isa junction.
 5. The semiconductor device according to claim 1, whereinthe first pulse, the second pulse, and the third pulse are different inpulse width from one another, the second pulse has the longest pulsewidth, and the third pulse has the shortest pulse width.
 6. Thesemiconductor device according to claim 1, wherein voltage of the thirdpulse is higher than that of the first pulse or the second pulse.
 7. Thesemiconductor device according to claim 1, wherein an amount of currentof the third pulse is more than that of the first pulse or the secondpulse.
 8. The semiconductor device according to claim 1, furthercomprising a CPU.
 9. A semiconductor device including a memory arraycomprising a plurality of memory cells provided at intersecting pointsof a plurality of word lines with a plurality of bit lines intersectingthe plurality of word lines via an insulating layer, each memory cellincluding an information memory section and a select element, whereinthe information memory section comprises a first electrode, a memoryelement, a semiconductor material, and a second electrode, and a p-njunction is present in an interface between the memory element and thesemiconductor material.
 10. The semiconductor device according to claim9, wherein the memory element is chalcogenide.
 11. The semiconductordevice according to claim 9, wherein the semiconductor material isn-type silicon.
 12. A semiconductor device including a memory arraycomprising a plurality of memory cells provided at intersecting pointsof a plurality of word lines with a plurality of bit lines intersectingthe plurality of word lines via an insulating layer, each memory cellincluding an information memory section and a select element, whereinthe information memory section comprises a first electrode, a memoryelement, a semiconductor material, and a second electrode, and anon-ohmic electric resistance is present in an interface between thememory element and the semiconductor material.
 13. The semiconductordevice according to claim 9, wherein the memory element is chalcogenide.